Own your
Artificial Intelligence
We have designed a new chip that dramatically lowers the barrier to create and serve frontier artificial intelligence
AI has a compute problem
We believe that AI has tremendous potential to move humanity forward, discover new science, and raise the overall quality of life towards abundance. For the first time in history, humanity has figured out a way to turn sand and sunlight into machines of scientific discovery.
But today, creating and serving frontier intelligence is prohibitively expensive to the point that only a handful of companies control it. When we looked deeper into why, we found that current approaches - from silicon to software - operate orders of magnitude above the theoretical minimum required to create and serve the same intelligence, to the point of being outright wasteful.
Baud exists to cure this waste, and approach the intelligence efficiency of the human brain and eventually go beyond.
Concretely, as of today, we have built two things:
- An arithmetic representation that losslessly eliminates multiplications and compresses neural networks both during forward and backward passes
- An ASIC architecture that trains and serves this representation more efficiently than incumbents*
*Comparison made at the same process node and memory bandwidth.
The reason for doing this is that in silicon, a multiplier's size and complexity scale quadratically with bit width, while an adder's scale only linearly. By trading multiplications for additions, we pack an order of magnitude more compute and memory into the same die area making our chip faster, less power hungry, and simpler to build.
Software is a major hurdle for ASIC adoption. It's pointless if engineers have to write custom kernels, training recipes, and inference frameworks for our chip instead of leveraging their existing code and the rich ecosystem around PyTorch. That's why, from day one, we're building a compiler that works with any PyTorch nn.module and supports torch.distributed, FSDP2, and tensor parallelism.
We are a small team of experienced chip designers and deep learning engineers with a tight focus to bring this chip to life and create the hardware and developer platform around it, so businesses of all sizes can own their artificial intelligence.
We have a demo where we trained a small model on our ASIC emulated on an FPGA and is currently running inference at 1000+ tokens per second on a single FPGA. You can check it out here.
Beta
Early access to our first cluster

We are opening early access to our first cluster. Supported workloads include:
- Pretraining and fine-tuning
- RL post-training
- Inference
It is the best way to learn how accelerated training and inference feel on a multiplier-free ASIC. Getting in early also means you will be reserving a spot for large amounts of compute capacity and helping us shape the platform as it matures.
uniquely suited for
Multimodal models
Vision, language, and audio in a single model.
World models
Learned simulators for planning and control.
Media generation
Image, video, and audio synthesis.
